1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a function of simultaneously clearing or presetting part of memory data.
2. Description of the Related Art
It is known that some conventional systems using semiconductor memory devices have a function of simultaneously clearing or presetting all the memory data. For example, in the image memory, such a function is frequently required, and the semiconductor memory devices having the above function are widely used.
However, in order to simultaneously clear the memory data of all the memory cells to "0" or preset them to "1", it is necessary to simultaneously set all the word lines into the selected state or to "1" level. For this reason, the current consumption will increase, and the peak current will increase, thereby generating the power source noise. The power source noise will affect peripheral circuits of the memory device and various devices in the system. Further, in order to simultaneously set all the word lines into the selected state, it is necessary to provided an additional circuit in the output stage of row decoder. The presence of the additional circuit causes the operation speed in the normal operation mode (in which a specified one of the memory cells is selected and data is written into or read out from the selected memory cell) to be delayed.
In the system using the semiconductor memory device, it is sometimes required to simultaneously clear the memory data of not all but part of the memory area to "0" or preset them to "1" at a high speed. For example, in the cache memory, it is necessary to clear valid bits in the tag section to "0" at the starting time of the system operation and specify that the contents of the cache memory are not correct in the initial condition. However, the prior art system using the semiconductor memory device cannot satisfy the above requirements.